IBM Claims World's Smallest SRAM Memory Cell

IBM and its joint development partners -- AMD, Freescale, STMicroelectronics, Toshiba and the College of Nanoscale Science and Engineering (CNSE) has announced the first working static random access memory (SRAM) for the 22 nanometer (nm) technology node.

The SRAM cell utilizes a conventional six-transistor design and has an area of 0.1um2, breaking the previous SRAM scaling barriers. Researchers achieved this breakthrough at CNSE of the University at Albany, State University of New York. IBM and its partners do much of their leading-edge semiconductor research at CNSE.

"We are working at the ultimate edge of what is possible -- progressing toward advanced, next-generation semiconductor technologies," said Dr. T.C. Chen, vice president of Science and Technology, IBM Research. "This new development is a critical achievement in the pursuit to continually drive miniaturization in microelectronics."

The researchers utilized high-NA immersion lithography to print the aggressive pattern dimensions and densities and fabricated the parts in its a state-of-the-art 300mm semiconductor research environment. Additional details of this achievement will be presented at the IEEE International Electron Devices (IEDM) annual technical meeting to be held in San Francisco, CA, December 15-17, 2008.